SPICE Model
PDK
Standard Cell
Gate-TR Mixed-Level Timing Analysis Solution
Identifies unique devices of the design and generates gate level circuit
Topology matching and channel connected extraction techniques
Timing characteristics of extracted gate-level cells are automatically characterized and used in Static Timing Analysis (STA) step
Built-in STA engine and SPICE netlist generation capability with back-annotated parasitics
Efficient critical path tracing at the full-chip level
Automatic critical path extraction with parasitics
On the fly custom cell characterization
Unified environment for STA & dynamic simulation
Custom cell characterization
Timing analysis of
mixed design
Re-characterization of standard cell
Timing analysis of CPU
datapaths/Digital IPs
